An instruction set architecture (ISA) is the abstract interface between a processor's hardware and the software it runs, as Arm defines itCITE:E1. This interface is the layer that determines how a chip and the code running on it communicate, which is why control over an ISA carries weight across the entire chip industry.
Arm charges chip makers an up-front licence fee for access to a design, then collects a royalty on every chip shipped once that design goes into production, with the royalty typically based on the price of the chipCITE:E2. Arm describes the incorporation process as one that often takes three to four years between licensing and the point a chip actually shipsCITE:E2. Built on this model over time, Arm's compute platform has shipped over 350 billion chips and reaches over 22 million developers, a footprint Arm says positions it to extend a common architecture and ecosystem from cloud infrastructure to the edgeCITE:E3.
RISC-V International makes its ratified ISA and extensions royalty-free and open building blocks, a structural contrast with Arm's paid licence-and-royalty modelCITE:E4. RISC-V International states it is wholly committed to design freedom, choice, and flexibility, and that it supports open architecture extensions to the RISC-V ISACITE:E5. Where Arm's model charges for access to a fixed design, RISC-V International's model is built around open extensibility of the base ISA itselfCITE:E4CITE:E5.
RISC-V International says it is concentrating on verticals where RISC-V holds distinct advantages rather than competing across the whole market at once. RISC-V International CEO Andrea Gallo named automotive, data center, edge AI, security, and space as the verticals where the organization is focusing its effortsCITE:E6.
RISC-V International ratified the RVA23 profile at the end of 2024 to give its ecosystem a common baseline for application processors running operating systems such as LinuxCITE:E7. Gallo described the ecosystem rallying around RVA23 in 2025 as a major step forward, noting that the profile defines a standard set of architectural features so that operating systems, compilers, libraries, and applications all have one clear target to aim atCITE:E7. For an open, extensible ISA, that single common baseline is the mechanism RISC-V International points to for containing the fragmentation risk that comes with allowing open architecture extensionsCITE:E5CITE:E7.
The two organizations are running different plays on the same layer of the stack. Arm's over 350 billion shipped chips and over 22 million developersCITE:E3 are the output of decades under a licence-fee-plus-royalty model where customers pay Arm for access and Arm collects a royalty per chip once shipments beginCITE:E2. RISC-V International's royalty-free, extensible ISACITE:E4CITE:E5 takes the opposite starting position, and rather than contesting Arm's installed base directly, RISC-V International is concentrating on automotive, data center, edge AI, security, and spaceCITE:E6, while using the RVA23 profile ratified at the end of 2024 to give that open, extensible model a common software targetCITE:E7.
An instruction set architecture (ISA) is the abstract interface between a processor's hardware and the software it runs, as Arm defines itCITE:E1.
Arm charges chip makers an up-front licence fee for access to a design, then collects a royalty on every chip shipped once that design goes into production, wit…
RISC-V International makes its ratified ISA and extensions royalty-free and open building blocks, a structural contrast with Arm's paid licence-and-royalty mode…
RISC-V International says it is concentrating on verticals where RISC-V holds distinct advantages rather than competing across the whole market at once.
The comparison here isn't feature-for-feature — it's business model versus business model. Arm's over 350 billion shipped chips and 22 million developers are the compounding output of a licence-fee-plus-royalty structure that has run for decades; that installed base and developer familiarity are themselves the moat, independent of any single technical edge. RISC-V International isn't trying to out-scale that in one move — it is deliberately narrowing to automotive, data center, edge AI, security, and space, and betting that a royalty-free, extensible ISA plus a unifying baseline like RVA23 can build defensible depth in those verticals before asking developers to standardize on one target the way Arm's ecosystem already has. The concrete thing to watch next is how much RVA23-compliant silicon and tooling actually ships into those named verticals — that adoption pace, not the openness of the standard itself, is what will show whether the vertical-focus strategy is converting into real share.
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