HBM High-Bandwidth Memory Generations (HBM2 to HBM4)
Specs across HBM generations (HBM2 / HBM2E / HBM3 / HBM3E / HBM4): per-pin data rate, per-stack bandwidth, max stack height and capacity. AI accelerator memory bottlenecks tie directly to HBM generation.
| Generation | JEDEC standard | Per-pin rate | Per-stack bandwidth | Max stack | Max capacity/stack | Year |
|---|---|---|---|---|---|---|
| HBM2 | JESD235A | 2.0 Gbps | 256 GB/s | 8-Hi | 8 GB | 2016 (std) |
| HBM2E | JESD235B | 2.4 Gbps | 307 GB/s | 12-Hi | 24 GB | 2018 (std) |
| HBM3 | JESD238 | 6.4 Gbps | 819 GB/s | 16-Hi | 64 GB | 2022 (std) |
| HBM3E * | Vendor ext. | 9.2–9.8 Gbps | ~1.2 TB/s | 12-Hi | 36 GB | 2024 (mass prod.) |
| HBM4 | JESD270-4 | 8 Gbps | 2 TB/s | 16-Hi | 64 GB | 2025 (std) |
Method & sources
Figures follow JEDEC official standards: HBM2=JESD235A, HBM2E=JESD235B, HBM3=JESD238, HBM4=JESD270-4 (published 2025-04). As jedec.org returns 403 to fetchers, JEDEC figures were confirmed via multiple tech outlets (Phoronix, Tom''s Hardware, WCCFTech, VideoCardz) citing the official text. ⚠ "HBM3E" is not an independent JEDEC standard but a vendor (Samsung/SK hynix/Micron) extension of HBM3; that row shows representative production-product specs (Samsung Shinebolt 9.8Gbps 36GB, SK 9.6Gbps, Micron >9.2Gbps), marked with *. The HBM4 row is the JEDEC baseline (8 Gbps/pin, 2 TB/s, 2048-bit interface); vendor HBM4 products run faster (Samsung ~11.7, Micron >11 Gbps, 2.8+ TB/s) — vendor specs, not the standard column. Years are standard-publication years (production year for HBM3E). Specs and supply change frequently; verify with official sources.
Source: https://www.jedec.org/
Retrieved: 2026-07-22