AMD (超微) pushed further into AI on July 23, headlined by the MI455X GPU and the sixth-generation EPYC CPU series — both built on TSMC's (台積電) 2-nanometer process — which together form AMD's Helios rack-scale solution, according to United Daily News (money.udn.com).
At the same event, AMD CEO Lisa Su formally presented the new Instinct MI400-series data-center AI accelerators, built on the CDNA 5 architecture and TSMC's 2nm process. The MI400 series comprises the MI430X and the higher-end MI455X, targeting HPC, sovereign AI, frontier model training, and large-scale inference infrastructure, per iThome (ithome.com.tw).
The MI455X is designed for large-scale model training and inference. iThome reports it uses a 2nm design paired with the CDNA 5 architecture and contains 320 billion transistors, while CNA (cna.com.tw) separately reported that Lisa Su described the same 320-billion-transistor chip as built "by TSMC's most advanced 2nm and 3nm processes" — the two outlets differ on whether a 3nm component is involved, but agree on the transistor count.
| MI455X spec | Value | Source |
|---|---|---|
| Transistors | 320 billion | iThome, CNA |
| Process | 2nm design (iThome) / "most advanced 2nm and 3nm" (CNA) | iThome, CNA |
| Max HBM4 memory | 432GB | iThome |
| Memory bandwidth | 23.3 TB/s | iThome |
| MXFP8 performance | 20 PF | iThome |
| MXFP4 performance | 40 PF | iThome |
| Token throughput vs. prior gen | up to 34x | UDN |
| Token cost vs. prior gen | down up to 18x | UDN |
UDN reported that AMD says MI455X's token throughput can reach up to 34 times that of the prior generation, while token cost can drop by up to 18 times.
UDN reported that the MI430X, aimed at sovereign AI and high-performance computing (HPC), delivers up to 288 TFLOPS of hardware-level FP64 performance for scientific computing needs.
iThome added timeline and comparison detail: MI430X is slated to launch in the first half of 2027, with FP64 HPC performance reaching 288 TF — 8.7 times higher than Nvidia's Vera Rubin, according to AMD. It also supports 432GB of HBM4 memory, 50% more capacity than Vera Rubin, with the same 23.3 TB/s memory bandwidth as the MI455X.
AMD announced in May 2026 that its sixth-generation EPYC Venice processor entered mass production — the industry's first HPC product mass-produced on TSMC's 2nm process, per UDN. iThome specified that Venice carries the model designation 9006 series and is now in mass production.
CNA added further detail from Lisa Su's presentation: Venice, built for AI agents, contains 203 billion transistors, uses TSMC's latest 2nm process and a next-generation chiplet architecture, and has entered full mass production — a transistor count not reported by UDN or iThome, and notably lower than the MI455X's 320 billion.
iThome reported AMD's performance claims for Venice across three deployment tiers: in general-purpose enterprise servers, Venice delivers 3.3 times the performance of Nvidia's Vera CPU; in AI host nodes within GPU servers, it delivers 1.8 times the tokens-per-second of Intel's Xeon 6960P on frontier models; and in CPU-server "sandbox" workloads, it delivers 2.8 times the agents-per-watt of Arm-based CPUs.
iThome detailed the Helios rack's hardware: the CPU side uses the sixth-generation EPYC with 96 high-frequency cores; the GPU side uses MI455X reaching 40 PF of FP4 compute; networking runs on Pensando and UALoE, connecting 72 GPUs with scale-up bandwidth of 260 TB/s.
Comparing Helios to Nvidia's Vera Rubin NVL72, iThome reported AMD's claims of 15% more AI compute, 50% more total memory capacity, 50% more scale-out network bandwidth, and up to 30% better dollar-per-token output economics. CNA independently quoted Lisa Su making a near-identical claim — "competition in the market right now is intense" — citing 15% more compute, 50% more HBM4 memory capacity and bandwidth, and 50% more scale-out bandwidth versus rivals. The 15%/50%/50% figures are consistent across both outlets.
| Helios vs. Vera Rubin NVL72 | AMD's claimed advantage | Source |
|---|---|---|
| AI compute | +15% | iThome, CNA |
| Total memory capacity | +50% | iThome, CNA |
| Scale-out network bandwidth | +50% | iThome, CNA |
| Dollar-per-token economics | up to +30% | iThome |
iThome reported that AMD claims the Helios rack has already been adopted by hyperscale AI operators including OpenAI, Meta, Anthropic, Microsoft, and Oracle.
CNA reported that Lisa Su announced Helios has entered full mass production, with shipments expected to begin in the third quarter and capacity continuing to expand in the fourth quarter — positioning the product to compete directly against Nvidia's Vera Rubin NVL72.
UDN reported that beyond this year's MI400 series, AMD previewed its data-center GPU roadmap: an MI500 series next year carrying next-generation HBM memory, followed by an MI600 series in 2028.
iThome added architectural detail: the 2027 Instinct MI500 series will use the CDNA 6 GPU architecture and next-generation HBM memory, with improved CPU scale-up connectivity and new copper and optical high-speed interconnects. The Instinct MI600 series, currently in development, follows in 2028.
| Generation | Timing | Key detail | Source |
|---|---|---|
| MI400 (MI430X/MI455X) | 2026 (current) | CDNA 5, TSMC 2nm | UDN, iThome |
| MI500 | 2027 | CDNA 6, next-gen HBM, new interconnects | UDN, iThome |
| MI600 | 2028 | In development | UDN, iThome |
iThome reported Lisa Su's assessment that data-center compute demand, once dominated by AI training, is now dominated by inference — with the ratio of inference to training compute demand at roughly 6:4 in 2026.
CNA reported a separate figure from the same event: monthly token usage has grown nearly 160-fold over the past two years.
iThome reported that AMD expects the data-center AI accelerator market to grow to $1.4 trillion by 2030.
CNA reported that, despite Lisa Su's optimistic tone on AI's outlook, investor concern over large AI spending — compounded by Middle East tensions pushing up oil prices — left chip stocks swinging on the day of the announcement. AMD's own shares closed down 2.29%, though CNA noted a rebound appeared in after-hours trading.
Across the three outlets, the numbers point to a distinct gap between AMD's product-cycle claims and its stock's reaction on announcement day. iThome and CNA both cite the same 15%/50%/50% compute-and-memory advantage AMD claims for Helios over Nvidia's Vera Rubin NVL72, and iThome's reported 8.7x FP64 edge for the still-unreleased MI430X extends that narrative into 2027. Layered onto AMD's own framing — inference now outweighing training at roughly 6:4 and monthly token usage up nearly 160-fold in two years, per iThome and CNA — the specification and market-size claims (up to $1.4 trillion by 2030) describe a company positioning for sustained AI-infrastructure demand. Yet CNA's same report notes AMD shares fell 2.29% on the day these claims were made, before a partial after-hours rebound — a reminder that the specs disclosed at the event and the stock's immediate move are two separate data points from the same day, not one.
AMD announced in May 2026 that EPYC Venice entered mass production, calling it the industry's first HPC product mass-produced on TSMC's 2nm process, according to United Daily News (money.udn.com). iThome separately reported the chip carries the model designation 9006 series.
According to CNA, AMD CEO Lisa Su announced Helios has entered full mass production, with shipments expected to begin in the third quarter and capacity expanding further in the fourth quarter.
iThome reported the MI430X is scheduled for launch in the first half of 2027, offering up to 288 TFLOPS of FP64 performance for HPC and sovereign AI workloads.
iThome reported that AMD claims Helios has been adopted by hyperscale AI operators OpenAI, Meta, Anthropic, Microsoft, and Oracle.
According to TechNews and China Times reports, Meta is preparing a $12 billion bond sale through a BlackRock-backed SPV for a Texas data center, with investors demanding yields above 7%—about 0.4 percentage points higher than Meta's October 2025 Hyperion deal. MoneyDJ reports Alphabet's Q2 free cash flow turned negative for the first time as capex surged, underscoring investor unease over AI spending.
According to a CNA report (carried also by CTS), Taiwan's King Slide (川湖) says its Houston plant will start mass production in the third quarter, while Chenbro (勤誠) has already opened a US NCT site in March and signed a Dallas plant deal in May, as both AI supply-chain suppliers post sharp first-half revenue gains.
According to CNA (中央社) and Technews (科技新報), new U.S. Section 301 tariffs took effect July 24, setting Taiwan's rate at 10% versus 12.5% for China and Japan. Taiwan Institute of Economic Research (台經院) president Chang Chien-yi called the outcome favorable, while analyst Liu Pei-chen said impact on Taiwan's chip sector is limited, with advanced nodes largely shielded and mature nodes more exposed to a pending overcapacity probe.