Conventional front-side power delivery forces power lines and signal lines to share the same back-end-of-line (BEOL) metal layers, and power interconnects now account for at least 20% of routing resources in that increasingly crowded network CITE:E1. As chip features continue to shrink, this shared layout leaves power and signal routing competing for the same limited space, according to imec CITE:E1.
Backside power delivery moves the entire power distribution network (PDN) to the back of the silicon wafer, decoupling it from the signal network CITE:E2. By separating the two networks onto opposite sides of the wafer, the front side is freed to handle signal routing exclusively while the back side carries power CITE:E2.
Intel's PowerVia test chip showed more than a 30% improvement in platform voltage droop and a 6% frequency gain, though this result came from a test chip rather than a shipping product CITE:E3. On TSMC's angstrom-class A16 node, backside power delivery dedicates all front-side routing resources to signals, which TSMC says improves logic density and performance and makes A16 suited to HPC products that combine complex signal routing with dense power delivery networks CITE:E6.
Intel has moved PowerVia into volume production on its 18A process node CITE:E4. The client product Panther Lake, built on 18A, began ramping to high-volume production this year, with the first SKU set to ship before the end of the year and broad market availability starting in January 2026 CITE:E4. Intel's Fab 52 in Arizona has also entered volume production on the 18A node CITE:E4.
TSMC's A16 process will combine its Super Power Rail backside power architecture with nanosheet (Gate-All-Around) transistors, with production planned for 2026 CITE:E5. TSMC describes A16 as its offering that pairs this backside power architecture directly with GAA transistor technology on a single roadmap milestone CITE:E5.
Backside power delivery requires extreme wafer thinning to just a few hundred nanometers of silicon in order to expose nanoscale through-silicon vias (nTSVs) and minimize their resistivity, according to imec CITE:E7. This thinning step is necessary specifically to make the nTSVs accessible and keep their electrical resistance low enough for the backside power network to function CITE:E7.
| Data Point | Figure | Entity |
|---|---|---|
| Front-side power interconnect routing share | ≥20% of routing resources | imec |
| PowerVia test chip voltage droop improvement | >30% | Intel |
| PowerVia test chip frequency gain | 6% | Intel |
| Panther Lake broad market availability | January 2026 | Intel |
| A16 planned production | 2026 | TSMC |
| Backside wafer thinning target | a few hundred nm of silicon | imec |
Imec's explainer frames the shift to backside power as a direct response to a routing bottleneck where power interconnects already claim at least 20% of front-side resources CITE:E1. Against that backdrop, Intel and TSMC are pursuing the same architectural fix on different timelines: Intel's PowerVia is already in volume production on 18A with Panther Lake ramping this year and reaching broad availability in January 2026 CITE:E4, while TSMC's Super Power Rail on A16 is planned for production in 2026 CITE:E5. Both companies' approaches still face the same underlying manufacturing constraint imec identifies — extreme wafer thinning to expose and lower the resistance of nanoscale through-silicon vias CITE:E7.
Conventional front-side power delivery forces power lines and signal lines to share the same back-end-of-line (BEOL) metal layers, and power interconnects now a…
Backside power delivery moves the entire power distribution network (PDN) to the back of the silicon wafer, decoupling it from the signal network CITE:E2.
Intel's PowerVia test chip showed more than a 30% improvement in platform voltage droop and a 6% frequency gain, though this result came from a test chip rather…
Intel has moved PowerVia into volume production on its 18A process node CITE:E4.
The two vendors' disclosed figures point to different maturity stages of the same architecture: Intel's 30%-plus droop improvement and 6% frequency gain come from a test chip, while its 18A volume production and Panther Lake ramp are the real production proof point that this architecture works at scale. TSMC's A16 pairing of Super Power Rail with nanosheet transistors is still a 2026 production plan, not yet a shipping node. The metric worth watching next is whether Intel publishes production-chip performance data for Panther Lake once broad availability starts in January 2026, since that would show whether the test-chip gains hold up outside a controlled test environment — and whether TSMC's 2026 A16 timeline stays on track as the wafer-thinning step imec describes moves from process development into volume manufacturing.
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