Why Data Movement, Not Compute, Is Now AI's Interconnect Bottleneck: Inside Co-Packaged Optics

Why has interconnect become the AI data center bottleneck?

Interconnect costs, not compute, now dominate traditional switch system economics. Broadcom states that pluggable optical transceivers consume approximately 50% of a traditional switch system's power and constitute more than 50% of its costCITE:E1. That split reframes the AI infrastructure problem: moving data between chips and across racks is no longer a secondary expense sitting beside compute, it is comparable in scale to compute itself within the switch layerCITE:E1.

How does co-packaged optics shorten the signal path to cut power draw?

Co-packaged optics (CPO) works by placing the silicon photonic engine directly next to the switch die instead of routing electrical signals to a separate pluggable module. NVIDIA explains that traditionally a signal has to travel 14-16 inches over printed circuit boards or copper wires before reaching the optics, whereas with co-packaged silicon photonics the signal path is less than half an inchCITE:E2. Shortening the electrical path this much is the physical mechanism behind CPO's power and signal-integrity gainsCITE:E2.

How do CPO products compare: Broadcom's Bailly versus NVIDIA's Quantum-X?

Broadcom and NVIDIA have each shipped a co-packaged optics product, and their published specifications show two different points on the same design curve. Broadcom's Bailly is described as the industry's first 51.2 Tbps co-packaged optics Ethernet switch platform, integrating eight silicon-photonics-based 6.4 Tbps optical engines with Broadcom's Tomahawk 5 switch chipCITE:E3. NVIDIA's Quantum-X Photonics InfiniBand switch, unveiled at GTC 2025, provides 144 ports of 800 Gb/s and is claimed to use 4x fewer lasers to deliver 3.5x more power efficiencyCITE:E5.

What is the core challenge in deploying CPO: laser reliability and repairability?

Integrating lasers into the package raises reliability and serviceability concerns, and NVIDIA's design addresses this by keeping lasers outside the sealed switch core. NVIDIA states that lasers reside on front-panel external laser source pluggable OSFP modules, enabling quick diagnosis and replacement while the switch core itself remains sealedCITE:E4. This split — pluggable, replaceable lasers paired with a sealed optical/electrical core — is presented as the mitigation for what NVIDIA identifies as one of CPO's biggest concernsCITE:E4.

How is TSMC advancing CPO toward commercial production?

TSMC, as reported by TrendForce, is developing COUPE (Compact Universal Photonic Engine), a platform that connects electronic circuits (EIC) directly to photonic circuits (PIC) on wafers using copper-to-copper and hybrid bonding techniques built on TSMC's SoIC technology, and that includes a 200G microring modulatorCITE:E6. TSMC's stated plan, per the same report, is to mass-produce semiconductors using this CPO technology by 2026CITE:E6. That places TSMC's foundry-level roadmap roughly a year or more behind the switch-level products Broadcom and NVIDIA have already announcedCITE:E3CITE:E5CITE:E6.

How does CPO reshape interconnect architecture for AI servers?

Marvell frames CPO as an architectural enabler rather than just a power-saving component. Marvell states that by enabling longer-reach and higher-density XPU-to-XPU connections than copper, CPO technology facilitates the development of high-performance, high-capacity scale-up AI serversCITE:E7. That positions CPO not only as a fix for the power and cost profile identified in the switch layerCITE:E1, but as infrastructure for how accelerator chips connect to each other at scaleCITE:E7.

What this means

Taken together, the evidence shows CPO moving on two separate timelines. Switch vendors have already shipped products against the cost and power problem Broadcom quantified — Bailly at 51.2 TbpsCITE:E3 and Quantum-X Photonics at 144 ports with a claimed 3.5x efficiency gainCITE:E5 — while TSMC's foundry-level COUPE platform, the piece that would let EIC-on-PIC bonding scale beyond individual switch vendors, is not targeted for mass production until 2026CITE:E6. At the same time, NVIDIA's own account of the laser-reliability challenge shows the current answer is a system-level workaround — pluggable external lasers around a sealed coreCITE:E4 — rather than a change to the underlying integration approach. Marvell's framing of CPO as enabling scale-up XPU-to-XPU architectureCITE:E7 suggests the interconnect shift is being built around AI accelerator topology specifically, not general-purpose networking.