DRAM stores each bit in a memory cell built from one transistor and one capacitor, with the capacitor's charge state encoding a 0 or a 1. Because that charge leaks over time, DRAM requires periodic refresh and loses all data once power is cut. The latest generational jump, DDR5, delivered a 50% bandwidth increase over DDR4 in its initial DIMMs.
What Circuit Makes Up a DRAM Memory Cell?
DRAM stores each bit of data in a memory cell built from exactly one transistor and one capacitorCITE:E1. Samsung Semiconductor describes the same structure, stating that each memory cell has a transistor and a capacitorCITE:E2. Micron Technology adds that this one-transistor, one-capacitor design is built for fast data access while a system is runningCITE:E1.
How Does the Capacitor's Charge Encode a 0 or a 1?
The capacitor in each cell distinguishes stored data by its charge level, representing the two basic digital data units, 0 and 1CITE:E3. Samsung Semiconductor states that the capacitor "saves data by distinguishing these two numbers" based on its chargeCITE:E3.
Why Does DRAM Need Periodic Refresh?
DRAM needs periodic refresh because the capacitor's stored charge leaks away over time, shortening how long it can hold dataCITE:E4. Samsung Semiconductor explains that "the capacitor's electrons short-circuit, shortening the time that it can maintain data," and that the capacitor is periodically refreshed to prevent thisCITE:E4.
What Does DRAM's Volatility Mean for Stored Data?
DRAM is volatile memory, meaning all saved data is deleted the instant power is turned offCITE:E5. Samsung Semiconductor states this directly: DRAM "has volatile memory that deletes the saved data once the power is turned off"CITE:E5.
How Much Bandwidth Did DDR5 Gain Over DDR4?
DDR5, the fifth generation of double data rate (DDR) memory technology, delivered a 50% bandwidth increase over DDR4 in its initial DIMMsCITE:E6CITE:E7. Rambus reports that DDR4 DIMMs top out at 3.2 gigatransfers per second (GT/s) at a clock rate of 1.6 gigahertz (GHz), while initial DDR5 DIMMs reached 4.8 GT/sCITE:E7.
| Generation | Peak Transfer Rate | Clock Rate | Change vs. Prior Generation |
|---|
| DDR4 | 3.2 GT/s | 1.6 GHz | — |
| DDR5 (initial DIMMs) | 4.8 GT/s | — | +50% |
This represents what happens after the underlying cell structure is fixed: the same one-transistor-one-capacitor design and the same refresh requirement carry forward from DDR4 into DDR5CITE:E1CITE:E4, while the interface generation moves the transfer rate from 3.2 GT/s to 4.8 GT/sCITE:E7. The physical constraints that define DRAM — a capacitor whose charge decays and must be refreshedCITE:E4, and a cell that is erased entirely when power is removedCITE:E5 — are unrelated to the DDR generational number; DDR5 solves for throughput, not for volatility or refresh dependency.
Author's Take・Nathan
The numbers here tell a consistent story: DRAM's speed advantage and its two defining weaknesses trace back to the same one-transistor-one-capacitor cell. That single capacitor is what lets DRAM read and write fast, but it's also why the charge leaks, why refresh cycles are mandatory, and why the whole array goes blank the moment power drops. DDR5's initial jump to 4.8 GT/s from DDR4's 3.2 GT/s ceiling is a 50% throughput gain, but it's an interface-layer improvement — it says nothing about whether refresh overhead or volatility exposure changes underneath it. The indicator worth watching in future DDR disclosures isn't just the next transfer-rate ceiling; it's whether generational updates ever report a change to the refresh mechanism itself, since none of the cited figures here touch that layer at all.