According to Intel's newsroom announcement, Intel's Fab 9 advanced packaging site in Rio Rancho, New Mexico has scaled its 'reticle limit' to 8 times the current industry standard, with a target of over 12 times by 2028. Intel says the facility grew from 25 employees in 1980 to 2,700 employees and 500 suppliers today, using Foveros and EMIB/EMIB-T technologies to package AI chips.
Intel's New Mexico Advanced Packaging Site: From 25 Employees to 2,700
According to Intel's newsroom, the company's Rio Rancho, New Mexico site — known as Fab 9 — has shifted from wafer manufacturing to advanced packaging over four decades. Katie Prouty, who manages the New Mexico advanced packaging site, says: "Back in the 1980s this site was the leader in 6-inch wafer manufacturing. Now over 40 years later, things have flipped and this site is the leader in the United States for advanced packaging."
Intel's newsroom also states that the site's workforce and supplier base have grown substantially since its founding:
| Metric | 1980 | Today (2026) |
|---|
| Employees | 25 | 2,700 |
| Suppliers | — | 500 |
As Intel puts it: "What started in Rio Rancho, New Mexico as 25 employees in 1980, has now proudly grown to 2,700 employees and 500 suppliers bringing critical U.S. advanced packaging technology to market."
Breaking the Reticle Limit: 8x Today, 12x+ by 2028
Intel's newsroom describes the Rio Rancho facility as expanding the "reticle limit" — the maximum size of a chip package that can be manufactured. Intel states: "advanced packaging technologies are expanding the 'reticle limit'—scaling packages to 8x the industry standard today, and over 12x by 2028."
| Timeframe | Reticle Limit vs. Industry Standard |
|---|
| Today (2026) | 8x |
| By 2028 (Intel target) | 12x+ |
Intel frames this reticle-limit expansion as a core part of enabling larger, more complex AI chip packages at the New Mexico site.
Foveros Packaging: Assembling Chiplets Like a 'Pizza'
According to Intel's newsroom, the company's Foveros advanced packaging process begins with a "chip attach tool." Chris Seibert, chief engineer at Intel's New Mexico Fab 9, describes the process using a food analogy: "Inside the fab, the chip attach tool is the first step in Intel's Foveros advanced packaging process. If we use a food analogy, this is the tool that brings in a 'pizza crust', or silicon wafer, and whatever 'pizza toppings' or specialized chiplets you want, we feed into the other side of this machine, and it attaches them to the top of that 'crust'."
Seibert says this process is designed to combine chips of different origins onto a single wafer: "The great part about that process is it lets us take a bunch of different chips from different designs or different technology nodes and put them all together onto one wafer."
EMIB and EMIB-T: Connecting Chips Without Costly Interposers
Intel's newsroom describes a second packaging technology, EMIB (Embedded Multi-Die Interconnect Bridge), as an alternative to silicon interposers used by other foundries. Intel states: "While other foundries might use expensive silicon interposers as the connection layer between chips, Intel Foundry embeds tiny, high-speed silicon bridges only where they're needed."
Intel's newsroom further states that in 2026, the company introduced an updated version called EMIB-T: "In 2026 the latest development is EMIB-T, which adds channels through that bridge to deliver power directly to the chips, instead of around it, which improves power efficiency and signal routing required by the latest high-bandwidth memory (HBM) technologies."
What This Means
According to Intel's own account, the same Rio Rancho site that led U.S. 6-inch wafer manufacturing in the 1980s is now the site Intel identifies as its U.S. advanced packaging leader, with its workforce expanding from 25 to 2,700 employees and its supplier network reaching 500 companies. That workforce growth parallels a technical roadmap Intel describes moving from an 8x reticle limit today to a 12x+ target by 2028, alongside two packaging methods — Foveros for multi-chiplet integration and EMIB/EMIB-T for interconnect and power delivery — that Intel says were both developed at this facility for AI chip production. The 2026 introduction of EMIB-T, per Intel's newsroom, is presented as an incremental update to the existing EMIB approach rather than a separate technology.