Intel describes PCI Express (PCIe) as a standards-based, point-to-point, serial interconnect used throughout the computing and embedded devices industriesCITE:E1. PCIe serves as the expansion interface connecting processors to devices such as graphics cards, SSDs, and network cards, per Intel's architecture documentationCITE:E1.
Intel specifies that PCIe links are expressed as x1, x2, x4, x8, x16, and so onCITE:E2. Under this scheme, a link's bandwidth is built by combining more lanes, with x1 representing the narrowest link and x16 representing the widest link Intel listsCITE:E2.
Synopsys states that PCIe 6.0 doubles the per-lane data rate from PCIe 5.0's 32 GT/s to 64 GT/sCITE:E3. Synopsys further states that PCIe 7.0, detailed in a June 13, 2024 post, delivers a 128 GT/s data rate and up to 512 GB/s of bidirectional bandwidth via an x16 linkCITE:E4.
| Generation | Per-Lane Data Rate | x16 Link Bandwidth | Source |
|---|---|---|---|
| PCIe 5.0 | 32 GT/s | — | SynopsysCITE:E3 |
| PCIe 6.0 | 64 GT/s | — | SynopsysCITE:E3 |
| PCIe 7.0 | 128 GT/s | Up to 512 GB/s (bidirectional) | SynopsysCITE:E4 |
| PCIe Gen 5 (NVIDIA Grace x16 link) | — | Up to 128 GB/s (bidirectional) | NVIDIACITE:E6 |
Synopsys states that PCIe 7.0's load-store capabilities and up to 512 GB/s of bandwidth for secure data transfers make it possible to connect multiple accelerators and process large, complex AI and machine learning models efficientlyCITE:E5. In a January 20, 2023 architecture post, NVIDIA states that each of the 8 PCIe Gen 5 x16 links in the NVIDIA Grace CPU Superchip supports up to 128 GB/s of bidirectional bandwidth, used to connect GPUs, network cards, and storage in data center systemsCITE:E6.
The evidence shows bandwidth scaling on two independent axes: lane width, from x1 to x16 as specified by IntelCITE:E2, and generational data rate, doubling from 32 GT/s to 64 GT/s to 128 GT/s across PCIe 5.0, 6.0, and 7.0 as specified by SynopsysCITE:E3CITE:E4. NVIDIA's Grace Superchip, shipping on PCIe Gen 5, already uses 8 separate x16 links at up to 128 GB/s each to connect GPUs, network cards, and storageCITE:E6, while Synopsys's PCIe 7.0 specification targets up to 512 GB/s on a single x16 link and frames that capacity around connecting multiple accelerators for AI and machine learning workloadsCITE:E4CITE:E5. Read together, the per-link ceiling Synopsys describes for PCIe 7.0 is four times the per-link bandwidth NVIDIA reports for the Gen 5 links already deployed in the Grace Superchip.
Intel describes PCI Express (PCIe) as a standards-based, point-to-point, serial interconnect used throughout the computing and embedded devices industriesCITE:E…
Intel specifies that PCIe links are expressed as x1, x2, x4, x8, x16, and so onCITE:E2.
Synopsys states that PCIe 6.0 doubles the per-lane data rate from PCIe 5.0's 32 GT/s to 64 GT/sCITE:E3. Synopsys further states that PCIe 7.
Synopsys states that PCIe 7.0's load-store capabilities and up to 512 GB/s of bandwidth for secure data transfers make it possible to connect multiple accelerat…
The two scaling levers in this evidence — lane width (x1 to x16) and generational data-rate doubling (32 to 64 to 128 GT/s) — are multiplicative, which is why a single PCIe 7.0 x16 link reaches the 512 GB/s figure Synopsys cites, four times the 128 GB/s NVIDIA reports per Gen 5 x16 link in the shipping Grace Superchip. Synopsys ties that 512 GB/s ceiling specifically to connecting multiple accelerators for AI and machine learning workloads, not to single-device throughput, which frames PCIe 7.0 as a multi-accelerator interconnect question rather than a single-GPU bandwidth question. The concrete thing to watch next is whether shipping multi-accelerator systems adopt PCIe 7.0 x16 links at the 512 GB/s level the way NVIDIA's Grace Superchip already adopted 8 separate Gen 5 x16 links at 128 GB/s each — that transition, not the spec number alone, is what would confirm the generational doubling actually reaches deployed hardware.
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