CXL, announced in early 2019, layers coherency protocols on PCIe 5.0, reaching 32 GT/s per direction; CXL 2.0 adds switching for memory pooling.
What is CXL (Compute Express Link), and when was it announced?
CXL Consortium defines Compute Express Link (CXL) as an industry-supported cache-coherent interconnect for processors, memory expansion, and acceleratorsCITE:E1. The interconnect now known as CXL was announced in early 2019CITE:E6.
How does CXL build on PCIe's physical and electrical interfaces?
CXL builds upon the physical and electrical interfaces of PCIe, adding protocols on top that establish coherencyCITE:E2. This means CXL does not replace PCIe's wiring and signaling — it reuses that foundation and layers coherency behavior above itCITE:E2.
What protocol layers does CXL define, and what does each cover?
CXL defines three distinct protocols: CXL.io, CXL.cache, and CXL.memCITE:E5. These three protocols together make up the CXL specification, running over the shared PCIe-based physical linkCITE:E5CITE:E2.
What are the performance specifications for CXL 1.1 and CXL 2.0?
CXL 1.1 and CXL 2.0 both use the PCIe 5.0 physical layerCITE:E3. The following figures summarize the throughput this physical layer delivers:
| Specification | Value |
|---|
| Physical layer used | PCIe 5.0CITE:E3 |
| Data transfer rate | 32 GT/sCITE:E3 |
| Maximum throughput per direction | Up to 64 GB/sCITE:E3 |
| Standard first announced | Early 2019CITE:E6 |
How does CXL's cache coherency improve efficiency and lower costs?
CXL Consortium states that CXL technology maintains memory coherency between the CPU memory space and memory on attached devicesCITE:E4. This coherency allows resource sharing that the consortium says delivers higher performance, reduced software stack complexity, and lower overall system costCITE:E4.
What does CXL 2.0's switching support mean for memory pooling?
CXL 2.0 supports switching to enable memory poolingCITE:E7. Switching is the specific mechanism CXL 2.0 adds beyond CXL 1.1 to make pooled memory possibleCITE:E7CITE:E3.
What this means
Across these sources, a consistent technical picture emerges: CXL keeps PCIe 5.0's physical layer and 32 GT/s (up to 64 GB/s per direction) signalingCITE:E3, adds three protocols — CXL.io, CXL.cache, and CXL.mem — on top of itCITE:E5, uses that combination to keep CPU and device memory coherentCITE:E4, and in the 2.0 revision extends this into switching-enabled memory poolingCITE:E7. The standard was announced in early 2019CITE:E6, and the coherency and pooling capabilities described here are what the consortium and technical publishers point to as its performance, complexity, and cost rationaleCITE:E4.
Author's Take・Nathan
The fact that CXL keeps the PCIe 5.0 physical layer while adding CXL.io, CXL.cache, and CXL.mem shows the consortium chose compatibility over a clean-sheet redesign, which is why the interconnect can reach 32 GT/s (up to 64 GB/s per direction) without new host silicon. The more consequential detail is that CXL 2.0 support for switching enables memory pooling, since pooling is what lets multiple hosts share disaggregated memory rather than each host being locked to its own attached capacity. That is the indicator worth tracking: how many CXL 2.0 deployments actually turn on switching-based pooling, versus how many merely use CXL 1.1 point-to-point memory expansion.