A photomask carries the circuit blueprint that lithography optics shrink onto silicon wafers at a 4× reduction. Extreme Ultraviolet Lithography (EUV) systems use reflective masks operating at a 13.5 nm wavelength, and a pellicle membrane shields those masks from contamination to reduce pattern defectivity, per ASML and imec technical documentation.
How does a photomask carry and project circuit patterns during lithography?
A photomask carries the pattern blueprint that lithography light passes through on its way to the waferCITE:E1. ASML describes the process as light projected through a blueprint of the pattern that will be printed, known as a "mask" or "reticle"CITE:E1. That blueprint is not printed at final size: the pattern on the mask is four times larger than the intended pattern on the chipCITE:E2. Once the pattern is encoded in the light, the lithography system's optics shrink and focus it onto a photosensitive silicon waferCITE:E3. In this sequence, the mask functions as the master copy, the 4× scaling sets the geometric relationship between mask and chip, and the optics perform the final reduction and focusing step onto the waferCITE:E1CITE:E2CITE:E3.
How do EUV photomasks differ optically from conventional masks?
EUV masks reflect light rather than transmitting it, a structural departure from the transmissive mask process described aboveCITE:E7. ASML states that Extreme Ultraviolet Lithography (EUV), a technology entirely unique to ASML, uses light with a wavelength of 13.5 nanometersCITE:E4. Intel's technical documentation specifies that EUV masks must reflect rather than transmit lightCITE:E7. Because the mask-to-wafer projection described in the prior section relies on light passing through the mask, the reflective requirement for EUV marks a distinct optical architecture tied specifically to the 13.5 nm wavelengthCITE:E4CITE:E7.
How does an EUV pellicle prevent contamination and improve yield?
A pellicle is a thin membrane that shields the photomask from contamination during high-volume manufacturingCITE:E5. imec defines the pellicle as the membrane used to protect the mask from contamination during high-volume semiconductor manufacturingCITE:E5. ASML, in a September 14, 2022 article, states that pellicles are used in chipmaking as a way of reducing pattern defectivityCITE:E6. Applied to the reflective EUV mask described above, the pellicle's contamination barrier functions as the mechanism that keeps the mask's reflected pattern free of defect-causing particlesCITE:E5CITE:E6.
What this means
Across the three stages described here, the photomask carries a 4×-scaled blueprint that lithography optics reduce onto the waferCITE:E2CITE:E3; EUV systems replace that transmissive path with a reflective mask operating at 13.5 nmCITE:E4CITE:E7; and the pellicle membrane protects that reflective mask from contamination to reduce pattern defectivityCITE:E5CITE:E6. Each stage depends on the one before it: the reflective requirement exists because of the EUV wavelength, and the pellicle's defectivity-reduction role exists because the reflective mask must remain contamination-free for the 4× pattern transfer to hold.
Author's Take・EffectStory 編輯部
The three facts here line up into a single dependency chain rather than three separate technical footnotes: a 4× mask-to-wafer reduction only holds if the mask's pattern reaches the wafer intact, the EUV path replaces transmission with reflection at 13.5 nm, and the pellicle exists specifically to keep that reflective surface free of defect-causing particles. In other words, the pellicle isn't a peripheral accessory to EUV — it's the component that lets the reflective-mask architecture actually deliver on the same fidelity that transmissive masks achieve through direct light passage. The indicator worth tracking from this evidence alone is defectivity outcomes tied to pellicle use, since ASML frames the pellicle's entire purpose around reducing pattern defects rather than any other function.