Process node labels such as "3nm" or "2nm" no longer describe any single physical transistor dimension. imec and IEEE Spectrum trace how the decoupling began once advanced nodes moved past simple gate-length scaling, and today a node number signals a generational jump in performance and energy efficiency rather than a measurable size on the chip.
Why did early process node names once match actual transistor dimensions?
imec states that in earlier technology generations, the nanometer figure in a node name genuinely described a physical feature of the transistorCITE:E1. In the 28-nanometer generation, 28 nanometers was the actual gate length of the MOS transistor used in that technologyCITE:E1. At that stage, naming a process by its number was not a marketing shorthand — it was a direct measurement.
When did node names decouple from physical size, and what drove it?
imec states that once the industry moved into advanced-node technologies, the number in a node name stopped corresponding directly to any physical feature of the transistorCITE:E2. imec adds that for nearly two decades it has been clear that pure dimensional scaling driven by Moore's Law is no longer the only indicator used to predict how CMOS process nodes evolveCITE:E7. In other words, the break was not sudden: the gap between a node's name and its physical geometry widened gradually as scaling itself stopped being the sole design driver.
Why can't modern advanced nodes like TSMC's N3 be defined by a single physical dimension?
imec points to TSMC's N3 technology as a concrete case: N3 uses 3D transistors, and in a 3D transistor structure, gate length is no longer relevant as a measurementCITE:E3. Once the transistor itself becomes a three-dimensional structure rather than a flat, planar one, there is no longer a single flat "gate length" number that a node name could accurately encode.
Do industry figures agree on what exact physical size a node number represents?
No single figure answers to a node number, according to Intel's own senior fellow Mark Bohr. As reported by IEEE Spectrum, a particular node name today does not reflect the size of any particular chip feature the way it once didCITE:E4. Bohr told IEEE Spectrum that he could not point to the one dimension that is 32 nanometers, 22 nanometers, or 14 nanometersCITE:E5. That admission came from an Intel senior fellow — not an outside critic — about Intel's own node names.
What does a node name actually represent today?
A node name today functions as a generational performance label rather than a physical measurement, as illustrated by GlobalFoundries. IEEE Spectrum reported that GlobalFoundries called a batch of chips "14-nm" because they delivered roughly a generation's-worth jump in performance and energy efficiency over the company's 20-nanometer chipsCITE:E6 — not because any feature on those chips measured 14 nanometers.
Node names compared: label versus what the evidence shows
| Node label | Who names it | What the evidence shows |
|---|
| 28 nm | imec (describing an earlier generation) | Matched the actual MOS transistor gate lengthCITE:E1 |
| 32 nm / 22 nm / 14 nm | Intel (Mark Bohr, via IEEE Spectrum) | No single dimension on the chip measures exactly thisCITE:E5 |
| 14 nm vs. 20 nm | GlobalFoundries (via IEEE Spectrum) | Named for a generation's-worth of performance/efficiency gain over the 20nm generation, not a physical shrinkCITE:E6 |
What this means: the record laid out by imec and IEEE Spectrum shows a consistent pattern rather than a single anomaly — the 28nm generation's name matched a physical gate lengthCITE:E1, but by the 32/22/14nm era Intel's own senior fellow could not map the name to any specific dimensionCITE:E5, and GlobalFoundries explicitly named a node for its generational performance and efficiency gain rather than its geometryCITE:E6. imec's account of TSMC's N3, where 3D transistors make gate length irrelevant as a metric, extends the same pattern into the current generationCITE:E3. Across three independent sources — imec, IEEE Spectrum's interview with Intel, and IEEE Spectrum's account of GlobalFoundries — the node number functions as a generational marker of relative progress, not a physical measurement.
Author's Take・EffectStory 編輯部
The strongest evidence in this record is not a critic's complaint but Intel's own admission: senior fellow Mark Bohr could not name the one dimension that equals 32nm, 22nm, or 14nm on Intel's own chips. That undercuts any reading of node numbers as engineering specifications — they function as generational shorthand, which is exactly how GlobalFoundries used "14nm" to signal a performance and efficiency jump over its 20nm generation rather than a measured shrink. imec's account of TSMC's N3 pushes the same logic further: once transistors become 3D structures, gate length itself stops being a meaningful single number to report. The indicator worth watching going forward is whether foundries and imec's own roadmap continue framing next-generation nodes (like 2nm-class technology) around relative performance and efficiency claims rather than any specific physical dimension — if that pattern holds, it confirms the node number has fully settled into a generational label rather than a spec.