Chip cost is governed primarily by yield — the share of good dies from a wafer batch — which falls as defect counts rise. Total die cost equals the cost of a good die plus assembly, adjusted by yield at final test. Yield itself follows a fixed relationship: critical area multiplied by defect density, meaning larger dies are structurally harder to keep defect-free. Cerebras addressed this on its 46,255 mm² wafer-scale chip by building in redundant cores tolerant of roughly 1% core failure, while Synopsys points to data-driven 'yield learning' as the ongoing lever for improving yield over a process's lifetime.
What Is Semiconductor Yield, and How Does It Relate to Defects?
Semiconductor yield is the share of good circuits produced in a batch, and it falls as the number of defects rises. The relationship is described directly: "The number of defects would rise, and the yield—the proportion of good circuits in the batch—would start to fall" CITE:E1. This inverse link between defect count and yield is the foundation for every cost and design tradeoff discussed below.
How Does Yield Directly Determine a Chip's Final Cost?
Yield acts as a direct multiplier on chip cost: total production cost is the cost of a good die plus the cost of assembly, modified by the yield measured at final test CITE:E2. Because the yield figure is applied on top of the die-and-assembly cost base, any drop in the proportion of good dies raises the effective cost of every chip that does ship.
How Do Defect Density and Die Area Together Determine Yield?
Critical area and defect density together set the expected defect count on a chip: the product of critical area and average defect density gives the expected number of fatal defects per circuit CITE:E3. This formula is the mechanical link between a chip's physical layout and how many of its dies will fail — it is also the reason die size and defect density cannot be considered separately when evaluating yield.
Why Does a Larger Die Area Make Yield Harder to Sustain?
A larger die area directly raises the odds of encountering a defect, since "the likelihood of there being a defect increases as the chip gets larger" CITE:E4. Combined with the critical-area formula above, this means that as chip designers push die size upward, the expected number of fatal defects per chip rises along with it, putting continuous downward pressure on yield.
Why Did Cerebras's Giant Chip Need Redundant Design?
Cerebras built its wafer-scale chip with redundant cores specifically to survive the defects that come with an extremely large die. Cerebras's single chip extends over 46,255 square millimeters, more than 50 times the size of other processor chips on the market CITE:E5. To offset the higher defect exposure that comes with that scale, Cerebras fit in enough redundant cores to account for the defect-induced failure of even 1 percent of them while still delivering a large, powerful chip CITE:E6.
| Metric | Value |
|---|
| Cerebras chip die area | 46,255 mm² |
| Size versus other processor chips | 50x+ larger |
| Redundant-core failure tolerance | ~1% of cores |
How Does Process Learning and Data Analysis Continuously Improve Yield?
Synopsys says data-driven analysis of silicon behavior can accelerate the "yield learning" process used to optimize a chip's final yield CITE:E7. That framing treats yield not as a fixed outcome of a given defect density and die area, but as a figure that can be pushed upward over time through analysis of production data.
What Does This Mean?
Taken together, the evidence traces a single chain: yield is defined by the ratio of good dies to total dies CITE:E1, that ratio is set mechanically by critical area multiplied by defect density CITE:E3, and larger die areas push the expected defect count up CITE:E4 — which is exactly the pressure Cerebras's 46,255 mm² chip faced and offset with cores tolerant of about 1% failure CITE:E5CITE:E6. Because yield is applied directly to die-and-assembly cost CITE:E2, the same defect-density-and-area relationship that forced Cerebras into redundant design is the reason Synopsys frames continuous "yield learning" from process data as an ongoing cost lever rather than a one-time fix CITE:E7.
Author's Take・EffectStory 編輯部
The numbers here point to redundancy as an architectural answer to a formula, not a workaround for it: once critical area times defect density sets the expected fatal-defect count on a die, a 46,255 mm² chip has no path to viable yield except designing around failure, which is exactly why Cerebras's approach was to absorb roughly 1% core loss rather than chase zero defects. That reframes 'yield' from a fab-only metric into a design decision made at the chip-architecture stage. The metric worth watching next is whether more large-die designs (AI accelerators, wafer-scale parts) publish redundancy tolerances the way Cerebras did, versus relying solely on the kind of yield-learning data cycles Synopsys describes to bring defect density down instead.