Advanced Packaging (CoWoS/SoIC): Capacity & Suppliers (2026)
TSMC CoWoS/SoIC versus ASE, Amkor, Samsung and Intel in advanced packaging. CoWoS — not logic wafers — is the real binding constraint on AI accelerators: the shortage is packaging and HBM, not the chip itself.
| Firm / tech | Packaging technology | 2026 capacity/scale | Position & caliber |
|---|---|---|---|
| TSMC CoWoS | 2.5D silicon interposer (CoWoS-S/-R/-L) | Est. ~120,000–140,000 wpm (official: doubled each year 2024→2025→2026) | Dominant leader; absolutes are TrendForce estimates, official gives only growth rates |
| TSMC SoIC | Wafer-level 3D hybrid bonding | Est. ~10,000–15,000 wpm (small base, CAGR>100%) | 3D-stacking workhorse; often combined as SoIC+CoWoS; not additive with CoWoS |
| Amkor | S-SWIFT / HDFO (CoWoS-S outsourcing) | Est. ~180,000–190,000 wafers/yr (annual basis) | Key non-TSMC-camp partner; incl. Arizona site |
| ASE / SPIL | CoWoP (in-house) + TSMC outsourcing | CoWoP target ~20,000–25,000 wpm by end-2026 | World's largest OSAT; second-tier advanced-packaging force |
| Samsung | I-Cube / H-Cube (2.5D), 3D Cube | Undisclosed (uncertain) | Integrates own foundry+HBM+packaging; 2.5D share far below TSMC |
| Intel Foundry | EMIB (2.5D bridge), Foveros (3D) | Undisclosed (uncertain) | Only IDM shipping 3D hybrid bonding; external packaging foundry nascent |
| UMC / PSMC | Interposer / wafer-on-wafer bonding (niche) | Undisclosed (uncertain) | New/niche entrants absorbing CoWoS spillover demand |
Method & sources
Retrieved 2026-08-28. **Key caliber warning: TSMC never discloses absolute CoWoS/SoIC monthly capacity (kwpm); earnings calls give only growth rates** (capacity doubled in 2024 and again in 2025; CoWoS to grow >60% over 2025 by 2027; CoWoS CAGR >80% for 2022–2027, SoIC CAGR >100% for 2022–2026). Every absolute wafer figure below (35k/75k/130k wpm, etc.) is therefore a **TrendForce-style industry estimate, not a TSMC-disclosed value**, marked "est." **Three traps isolated**: (1) monthly wpm vs annual-wafer bases must not be mixed (Nvidia ~595k wafers and Amkor ~180–190k wafers are annual, ~12x apart from monthly); (2) CoWoS is a family (S/R/L) — the aggregate is not comparable to a single sub-type; (3) CoWoS (2.5D interposer, ~100k wpm scale) and SoIC (wafer-level 3D hybrid bonding, ~10k wpm scale) are different processes and cannot be summed. Samsung/Intel/UMC/PSMC **capacity is uncertain (undisclosed)** — only their technology names/roadmaps are officially sourced. Sources: TrendForce https://www.trendforce.com/news/2026/06/15/news-tsmc-cowos-supply-demand-gap-reportedly-seen-narrowing-from-20-to-10-by-end-2026-as-capacity-expands/ ; Epoch AI https://epoch.ai/data-insights/ai-chip-supply-chain-constraints .
Retrieved: 2026-08-28
FAQ
- What does "Advanced Packaging (CoWoS/SoIC): Capacity & Suppliers (2026)" cover?
- It covers TSMC CoWoS, TSMC SoIC, Amkor, ASE / SPIL, Samsung, Intel Foundry, UMC / PSMC, compared across: Firm / tech, Packaging technology, 2026 capacity/scale, Position & caliber.
- What are the sources and methodology?
- Retrieved 2026-08-28.
- When was this data last updated?
- The data was retrieved/updated on 2026-08-28.