Planar NAND flash hit a physical ceiling below 20 nanometers, capping density at 128 Gb per die, which pushed the industry to build upward instead of shrinking further. Samsung Semiconductor's V-NAND raised the density limit to 1 Terabit, Kioxia scaled its BiCS FLASH from 48 layers in 2015 to 162 layers in 2022, and Micron shipped the industry's first 232-layer 3D NAND the same year. Alongside stacking, QLC cell encoding raised per-cell storage from three bits to four, adding a second, independent density lever.
When Did Planar NAND Scaling Hit Its Physical Limit?
Samsung Semiconductor states that once memory cells shrink below 20 nanometers, the probability of electrical charge leaking from one cell to another increases significantlyCITE:E3. This charge-leakage risk marked one of the physical limits of two-dimensional, or planar, scaling. Samsung Semiconductor further notes that planar NAND design tops out at a maximum component density of 128 GbCITE:E5, leaving no further room to add capacity by shrinking cells within a single flat layer.
How Did Vertical Stacking Break Through the Planar Scaling Bottleneck?
Samsung Semiconductor's V-NAND design stops trying to squeeze more cells into a shrinking area and instead builds upward, stacking cells on top of one anotherCITE:E4. Micron describes the same underlying principle at an industry level: stacking the NAND bit cell array into more layers provides more bits per square millimeter of silicon, allowing greater density and lower cost per bitCITE:E1. By moving into the vertical dimension, Samsung Semiconductor's V-NAND structure expands the maximum density limit from planar NAND's 128 Gb to 1 TerabitCITE:E5.
How Has the Industry Advanced Layer Counts Generation by Generation?
Kioxia has commercialized four successive generations of its BiCS FLASH product line, rising from 48 layers in 2015 to 162 layers in 2022CITE:E6. Micron extended that same trajectory further, announcing the industry's first 232-layer 3D NAND in 2022, which debuted shipping on selected Crucial-branded SSDsCITE:E2.
| Year | Product / Generation | Layer Count |
|---|
| 2015 | Kioxia BiCS FLASH | 48 |
| 2018 | Kioxia BiCS FLASH | 96 |
| 2020 | Kioxia BiCS FLASH | 112 |
| 2022 | Kioxia BiCS FLASH | 162 |
| 2022 | Micron 3D NAND | 232 |
How Does Multi-Bit Cell Encoding Further Increase Storage Density?
Kioxia's QLC technology raises the number of bits stored per memory cell from three, used in TLC, to fourCITE:E7. Kioxia states that this increase in bit count per cell significantly expands capacity, offering a density gain that operates independently of how many layers are stackedCITE:E7.
What does this mean?
The record shows two density levers advancing on separate tracks within the same industry timeframe. In 2022 alone, Kioxia's 162-layer BiCS FLASHCITE:E6 and Micron's 232-layer 3D NANDCITE:E2 both shipped, while Samsung Semiconductor's V-NAND had already redefined the achievable density ceiling from planar NAND's 128 Gb to 1 TerabitCITE:E5. Layered on top of that vertical progress, Kioxia's QLC shift from three bits to four bits per cellCITE:E7 adds a second, independent axis of capacity gain — meaning stacking height and per-cell bit depth are two distinct variables that together, not separately, determine total NAND density.