According to TrendForce, the global AI optical transceiver market is forecast to grow from $16.5 billion in 2025 to $26 billion in 2026, up more than 57%, as North American hyperscale data center traffic keeps expanding above 30% a year. Morgan Stanley separately projects co-packaged optics (CPO) revenue rising from $8 million in 2023 to $9.3 billion by 2030, with NVIDIA-linked designs reaching 75% of that demand by 2027, even as TrendForce flags tight EML and CW-LD chip supply.
How big is the AI optical transceiver market, and what is driving the demand?
TrendForce forecasts that the global market for AI-dedicated optical transceivers will expand from $16.5 billion in 2025 to $26 billion in 2026, a year-on-year increase of more than 57%. The research firm attributes this to sustained infrastructure buildout: North American hyperscale data center traffic has been growing at more than 30% annually, prompting Google, Microsoft, and Meta to keep adding GPUs and AI servers, according to TrendForce.
A parallel forecast from Morgan Stanley, cited by Bnext, zooms in on the co-packaged optics (CPO) segment specifically: global CPO market size is projected to grow from $8 million in 2023 to $9.3 billion by 2030, a compound annual growth rate of 172%. Morgan Stanley further expects NVIDIA-related platforms — including the Rubin successor to Blackwell and NVL rack systems — to account for 75% of global CPO demand by 2027, citing higher CPO adoption visibility and a greater proportion of CPO usage per system.
| Market | Base Year | Base Value | Target Year | Target Value | Growth |
|---|
| AI optical transceivers (TrendForce) | 2025 | $16.5B | 2026 | $26B | +57% YoY |
| CPO (Morgan Stanley) | 2023 | $8M | 2030 | $9.3B | 172% CAGR |
Why is the industry shifting toward LPO and silicon photonics integration?
TrendForce reports that technology roadmaps are "accelerating" toward low-power linear pluggable optics (LPO) and silicon photonics integration, aiming to replace traditional high-power DSP (digital signal processor) architectures and ease power and thermal pressure on system design.
The rationale becomes clearer when comparing bandwidth ceilings across optical integration architectures. Citing ASE Technology (日月光) data, Bnext reports that pluggable transceivers top out at 100/400/800G, on-board optics (OBO) packaging reaches up to 800G and 1.6T, co-packaged optics (CPO) spans 3.2T to 12.8T, and optical input/output reaches 6.4T, 12.8T and beyond.
| Architecture | Maximum Bandwidth |
|---|
| Pluggable transceiver | 100/400/800G |
| On-board optics (OBO) | up to 800G / 1.6T |
| Co-packaged optics (CPO) | 3.2T–12.8T |
| Optical I/O | 6.4T, 12.8T and above |
Neil Shah, Vice President at Counterpoint Research, framed the shift in strategic terms: "AI infrastructure is moving toward higher bandwidth, higher energy efficiency, and greater computing scale, and optical interconnect and silicon photonics will become an indispensable technology within that," he told TrendForce.
What progress have TSMC (台積電) and 波若威 (3163) made on CPO/COUPE, and who are the first customers?
TSMC (台積電) is advancing on two tracks, according to Bnext. As of 2024 reporting, TSMC expected to complete validation of its small-form-factor COUPE connector in 2025, then integrate it as a CPO component into CoWoS packaging in 2026, bringing optical links directly into the package. In an August 11, 2025 report, Bnext added that TSMC is pushing its CPO timeline forward at the request of two major AI chip customers, targeting mass production next year, primarily using an optical-engine-on-substrate (OE on Substrate) approach.
Analyst Ming-Chi Kuo (郭明錤) of TF International Securities (天風國際證券), cited by Bnext in a January 2025 note, laid out a two-generation COUPE timeline: the first generation had its specification finalized and began sample shipments in Q4 2024, will undergo validation from 2025 through the second half of 2026, and enter mass production in the second half of 2026. The second generation is expected to have its specification finalized and begin sampling in the first half of 2026, undergo validation from H1 2026 through H2 2027, and reach mass production between Q4 2027 and Q1 2028.
| Generation | Spec Finalized / Sampling | Validation Window | Mass Production |
|---|
| Gen 1 | Q4 2024 | 2025 – H2 2026 | H2 2026 |
| Gen 2 | H1 2026 | H1 2026 – H2 2027 | Q4 2027 – Q1 2028 |
On customers, Kuo expects AMD — which he notes has been aggressively adopting new technologies such as SoIC and 2nm — to be TSMC's first major COUPE customer. For NVIDIA, Kuo said the Rubin Ultra platform, slated for mass production at the end of 2027, is more likely than earlier NVIDIA products to be the first to adopt COUPE.
Elsewhere in the supply chain, 波若威 (3163), described by Bnext as Taiwan's largest fiber-optic passive-component contract manufacturer, told an earnings call on March 18 that it is building out CPO capability, with validation and small-batch shipments expected in the second half of 2025 and mass production to begin next year.
What bottlenecks constrain expansion, and how is NVIDIA adjusting procurement?
TrendForce identifies three constraints on scaling transceiver output: tight supply of key optoelectronic chips — specifically EML (electro-absorption modulated laser) and CW-LD (continuous-wave laser diode) components — stemming from capacity allocation issues; limits on high-precision optical alignment process capability; and ongoing power-and-thermal design challenges affecting system integration and rollout pace.
In response, TrendForce reports that upstream suppliers and system vendors led by NVIDIA have adjusted their procurement model, introducing strategic long-term contracts to lock in key materials and gradually reduce reliance on spot-market purchasing.
What this means
The two market forecasts point in the same direction at different scales: TrendForce's 57% year-on-year jump in overall AI optical transceiver revenue for 2026 and Morgan Stanley's 172% CAGR for the narrower CPO segment through 2030 both describe a market scaling from a small base. That scaling pressure lines up with TrendForce's own account of the bottleneck — EML and CW-LD chip supply constraints and optical alignment process limits — which is presumably why NVIDIA and other buyers, per TrendForce, have moved to lock in supply through long-term contracts rather than the spot market. On the technology side, the bandwidth gap Bnext reports between pluggable optics (capped at 800G) and CPO (up to 12.8T) helps explain why TrendForce describes the industry as accelerating toward LPO and silicon photonics rather than continuing to scale DSP-based designs. Meanwhile, the commercialization timelines from TSMC, Ming-Chi Kuo, and 波若威 span 2025 through 2028 — from COUPE validation and 波若威's small-batch shipments in 2025, to TSMC's CoWoS integration and first mass production in 2026, to a second COUPE generation not reaching mass production until early 2028 — suggesting the CPO transition Morgan Stanley models as a 2023–2030 curve is still in its early, multi-year build-out phase rather than at commercial scale today.