DDR5 is the fifth-generation double data rate (DDR) random-access memory (RAM) technology, Micron statesCITE:E1. As the successor in the DDR line, it is the current generation JEDEC-defined standard that memory vendors including Micron, Rambus, and Samsung build products aroundCITE:E1.
DDR5 chipsets support a ladder of data rates from 4,800 MT/s up to 9,600 MT/s, well beyond DDR4's ceiling, Rambus reportsCITE:E6.
| Metric | Value | Source |
|---|---|---|
| Entry-level data rate | 4,800 MT/s | RambusCITE:E6 |
| Gen3 data rate vs. Gen1 4,800 MT/s | 6,400 MT/s (+33% data rate and bandwidth) | RambusCITE:E5 |
| Full chipset data-rate range | 4,800 / 5,600 / 6,400 / 7,200 / 8,000 / 9,600 MT/s | RambusCITE:E6 |
| Per-pin speed | up to 8,000 Mbps | SamsungCITE:E7 |
| Max density | up to 32 Gb | SamsungCITE:E7 |
| Operating voltage | 1.1V (DDR4: 1.2V) | MicronCITE:E4 |
Rambus says its third-generation 6,400 MT/s DDR5 Registering Clock Driver (RCD) delivers a 33% increase in data rate and bandwidth over its first-generation 4,800 MT/s solutions, which it says "enables a new level of main memory performance for data center servers"CITE:E5. Separately, Samsung says its DDR5 chips reach per-pin speeds of up to 8,000 Mbps and densities of up to 32 GbCITE:E7.
DDR5 operates at 1.1 volts, down from 1.2 volts for DDR4, Micron statesCITE:E4. Micron describes this as "a meaningful reduction in power consumption per bit when used at scale"CITE:E4.
Micron builds DDR5 server memory with the power management IC (PMIC) integrated onto the module itself, moving power management onto the module rather than the motherboardCITE:E2. Micron also says DDR5 modules use dual independent channels per DIMM, which it says improves data handling and multitasking compared to DDR4CITE:E3.
Samsung's DDR5 chips include on-die error-correcting code (ECC) built into the chip, which the company says ensures improved signal integrity and stable operationCITE:E7. Samsung ties this reliability feature to the same generation of chips that reach up to 8,000 Mbps per pin and densities up to 32 GbCITE:E7.
Across the three vendors' documentation, DDR5's gains are not a single change but a stack of them: JEDEC's data-rate ladder runs from 4,800 MT/s up to a chipset-supported 9,600 MT/sCITE:E6, while Rambus's own Gen1-to-Gen3 RCD transition accounts for a documented 33% slice of that range at 6,400 MT/sCITE:E5. That speed scaling is paired with a voltage drop from 1.2V to 1.1VCITE:E4, a PMIC relocated onto the moduleCITE:E2, dual independent channels per DIMMCITE:E3, and on-die ECC protecting chips that reach 32 Gb density and 8,000 Mbps per pinCITE:E7. Each vendor's disclosure covers a different layer of the same standard, and together they show the improvements are distributed across voltage, architecture, and clocking rather than concentrated in one spec line.
DDR5 is the fifth-generation double data rate (DDR) random-access memory (RAM) technology, Micron statesCITE:E1.
DDR5 chipsets support a ladder of data rates from 4,800 MT/s up to 9,600 MT/s, well beyond DDR4's ceiling, Rambus reportsCITE:E6.
DDR5 operates at 1.1 volts, down from 1.2 volts for DDR4, Micron statesCITE:E4.
Micron builds DDR5 server memory with the power management IC (PMIC) integrated onto the module itself, moving power management onto the module rather than the …
The gap between DDR5's documented entry point of 4,800 MT/s and its chipset-supported ceiling of 9,600 MT/s is wider than the single 33% jump Rambus reports between its Gen1 and Gen3 RCDs at 6,400 MT/s, which suggests most of the standard's remaining headroom still depends on registering-clock-driver generations catching up to what the spec ladder already allows. Architecturally, moving the PMIC onto the DIMM and building ECC on-die shifts two reliability-critical functions from the motherboard and memory controller onto the module itself, putting more of DDR5's power and error-correction behavior under the memory vendor's own control. Worth watching is how quickly RCD chipsets move past the 6,400 MT/s Gen3 milestone toward the 9,600 MT/s ceiling Rambus already lists as supported, since that gap is where the next real-world performance jump sits.
Google announced a €13 billion ($15.1 billion) investment in Finnish AI infrastructure to be deployed in 2027–2028, its largest single investment in Europe. The plan covers new data centers in Kajaani, Muhos, and Vaala plus an expansion in Hamina, backed by a 22-year power deal for 50% of Loviisa nuclear plant output and projected to support 37,000 construction-phase jobs and 7,000 permanent roles.
Chenbro (勤誠, 8210) reported August 2026 revenue of NT$2.457 billion, roughly flat month-on-month (-0.2%) but up 40.5% from a year earlier. Cumulative January–August revenue reached NT$19.848 billion, up 51.7% year-on-year.
Chang Hwa Bank (TWSE: 2801) reported cumulative after-tax profit of NT$15.567 billion for January through August, up 23.21% year-on-year with EPS of NT$1.29, a record for the period. The bank attributed the gain to loan, deposit, and wealth management momentum, and August alone delivered NT$2.916 billion in profit, up 29.16% year-on-year.