IBM built what it calls the first dual-architecture mainframe processor ever made, with cores that execute either z/Architecture or AArch64 instructions natively rather than through emulationCITE:E1. Each of the chip's 11 cores can dynamically switch between Arm software mode and traditional Z software mode, and that switch happens at roughly the nanosecond scaleCITE:E2. IBM's Christian Jacobi described the design as a core that can execute either instruction set and flip between them dynamically "within nanoseconds"CITE:E10.
The chip is fabricated on a 2-nanometer process node and runs its 11 high-performance cores at a base frequency above 5.7 GHzCITE:E3. It carries the same 36 MB of private L2 cache as its predecessor, but its virtual L3 and L4 caches are larger — 432 MB of virtual L3 and 3.5 GB of virtual L4CITE:E12. For comparison, IBM's current Telum II processor, introduced in 2024, has eight cores running at up to 5.5 GHzCITE:E13.
| Metric | New dual-ISA chip | Telum II (2024) |
|---|---|---|
| Process node | 2nmCITE:E3 | — |
| Core count | 11CITE:E3 | 8CITE:E13 |
| Frequency | Base above 5.7 GHzCITE:E3 | Up to 5.5 GHzCITE:E13 |
| Private L2 cache | 36MBCITE:E12 | 36MBCITE:E12 |
| Virtual L3 / L4 cache | 432MB / 3.5GBCITE:E12 | Smaller (unspecified)CITE:E12 |
The processor implements a full hardware version of AArch64 v9.3, including Scalable Vector Extension support, covering 2,792 AArch64 instructionsCITE:E15.
IBM is adding Arm compatibility as hyperscale computing increasingly runs on Arm-based silicon and enterprises struggle to move AI pilots into full production. By Arm's own estimates, close to half of the compute shipped to major hyperscalers in 2025 was Arm-based, driven by AWS Graviton, Google Axion, and Microsoft's Arm silicon, and Arm counts more than 22 million developers worldwideCITE:E4. On the demand side, McKinsey's most recent State of AI survey found that 88% of organizations now use AI in at least one business function, but nearly two-thirds have not yet scaled it across the enterpriseCITE:E8.
IBM is carrying its high-availability claims onto the dual-ISA chip, though the two figures reported differ. IBM's Tina Tarquinio said the line delivers "eight nines of availability" — 0.3 seconds of downtime a yearCITE:E5, a figure reported by VentureBeat. Tom's Hardware separately reported IBM claiming 99.999999% uptime for the new processor, which it said equates to just 0.032 seconds of downtime per yearCITE:E11.
IBM is pairing the mainframe chip with a next-generation Spyre accelerator built for agentic large-language-model workloads. Christian Jacobi said IBM is "bringing a much higher performance chip that is capable of running large language models for agentic workflows," with the new accelerator shipping with high-bandwidth memory to feed those modelsCITE:E7. The new Spyre accelerator has 16 cores with optimizations for newer AI data formats including FP4/MXFP4, and each accelerator carries 96 GB of HBM3e memory offering up to 4TB/s of bandwidth — 20 times what IBM's LPDDR5-based predecessor deliveredCITE:E14.
The dual-ISA chip will debut in the successor to the z17, which shipped in the second quarter of 2025; holding to its roughly three-year product cadence, IBM's next mainframe generation points to a launch around 2028CITE:E6. IBM generally ships new mainframes every two and a half to three years, and the z17 itself was revealed in 2024 at Hot ChipsCITE:E16. Tina Tarquinio framed the Arm addition as complementary rather than a replacement: "This is a big and. It is not an or," adding that she has a roadmap extending 10 to 15 years for hardware systemsCITE:E9.
Taken together, the specs and the schedule point in the same direction: IBM is stacking more cores, cache, and a second instruction set onto the same reliability targets it has long marketed for Z, while pairing the CPU with a separately upgraded Spyre accelerator for LLM workloadsCITE:E3CITE:E12CITE:E14. Whether the eight-nines claim lands at 0.3 seconds or 0.032 seconds of yearly downtime depends on which report is cited, but both describe the same order-of-magnitude availability target IBM has held for the Z lineCITE:E5CITE:E11. The 2028 timeline built from the z17's 2025 shipment date and IBM's own two-and-a-half-to-three-year cadence gives a concrete window for when Arm-on-Z silicon actually reaches customersCITE:E6CITE:E16.
IBM built what it calls the first dual-architecture mainframe processor ever made, with cores that execute either z/Architecture or AArch64 instructions nativel…
The chip is fabricated on a 2-nanometer process node and runs its 11 high-performance cores at a base frequency above 5.7 GHzCITE:E3.
The processor implements a full hardware version of AArch64 v9.3, including Scalable Vector Extension support, covering 2,792 AArch64 instructionsCITE:E15.
IBM is adding Arm compatibility as hyperscale computing increasingly runs on Arm-based silicon and enterprises struggle to move AI pilots into full production.
The nanosecond-scale switch between z/Architecture and AArch64 mode is the harder engineering claim here, not the process-node bump — running a single physical core across two instruction sets while still targeting eight-nines-class availability means the switch logic has to hold up under IBM's usual failure-tolerance bar. Pairing that switch with 432 MB of virtual L3 and 3.5 GB of virtual L4 cache suggests IBM expects Arm-side workloads to be memory-hungry, not just instruction-compatible. None of that is testable from a Hot Chips announcement, though — it depends on whether real AArch64 software can actually exploit that cache hierarchy across all 2,792 supported instructions once the z17 successor ships around 2028. That's the metric worth tracking next: benchmarked dual-ISA performance on shipping silicon, not the specs disclosed today.
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