How Through-Silicon Vias Power 3D IC Stacking, From HBM3E's 12-Layer DRAM to 2µm Hybrid Bonding

What Is a Through-Silicon Via (TSV)?

A through-silicon via (TSV) is a vertical structure that creates an electrical connection through a die or waferCITE:E1. Lam Research describes TSVs as the physical channel that lets current and signals pass directly through silicon rather than around it, which is the basic mechanism that later sections show being used to stack multiple chips on top of one another.

Why Are Chipmakers Turning to 3D Stacking?

imec frames three-dimensional stacking of integrated circuits as one way to further extend IC scalingCITE:E2. As transistor-level shrinking becomes harder to sustain, imec's framing points to stacking dies vertically as an alternative path to keep adding performance and density, a direction that the HBM3E case below puts into practice.

How Does HBM3E Use TSV to Stack 12 DRAM Layers?

Samsung Semiconductor stacks 12 layers of 24Gb DRAM chips using TSV technology to build its HBM3ECITE:E3. The company states that this strategic stacking gives HBM3E its bandwidth and what it calls an "industry-leading" 36GB of capacity per layerCITE:E3.

How Fast Is HBM3E's Data Performance?

HBM3E reaches a data rate of 9.8Gbps per pin, which Samsung Semiconductor says translates into an overall performance speed of 1,250GB/sCITE:E4. These figures describe the same 12-layer, TSV-stacked DRAM structure covered above, showing how the vertical interconnect architecture converts into throughput.

How Fine Can Interconnect Pitch Get in 3D Integration?

imec is developing die-to-wafer hybrid bonding with interconnect pitches down to 2µm, paired with high-tolerance pick-and-place accuracyCITE:E5. This is a separate, finer-pitch bonding approach from the TSV stacking used in HBM3E, aimed at high-density three-dimensional integration.

How Do Packaging Providers Apply These Techniques in Practice?

Amkor Technology says its packaging solutions achieve performance by interconnecting logic chips and high-bandwidth memory in close proximityCITE:E6. Amkor published this description on May 25, 2024, framing close-proximity logic-to-HBM interconnection as the basis of its packaging approachCITE:E6.

HBM3E and 3D Integration Metrics at a Glance

What This Means

The vertical electrical connection that Lam Research defines as a TSVCITE:E1 is the same mechanism Samsung Semiconductor uses to physically build the 12-layer, 24Gb DRAM stack in HBM3ECITE:E3, which converts into the 9.8Gbps-per-pin and 1,250GB/s figures the company reportsCITE:E4. imec's broader case for 3D stacking as a way to extend IC scalingCITE:E2 is being pursued along two distinct paths in this evidence set: imec's own die-to-wafer hybrid bonding at pitches down to 2µmCITE:E5, and Amkor's package-level approach of placing logic chips and HBM in close proximityCITE:E6. Together, these sources describe vertical stacking and tight interconnection as complementary techniques operating at different structural levels — inside the memory stack and at the package level.