Process node names have not corresponded to any single physical transistor dimension since roughly the 22nm generation, and the number in a node name today functions mainly as a marketing label for a manufacturing generation rather than an actual nanometer measurementCITE:E1. Before that point, "Nnm" described a real physical feature such as gate length; after it, each foundry's naming scheme diverged from any shared physical standardCITE:E1.
A smaller node number generally points to higher transistor density and better power efficiency — either faster performance at the same power draw, or the same performance at lower powerCITE:E2. But because node naming is decoupled from physical size, a "2nm" chip from one foundry is not guaranteed to match another foundry's density or efficiency; the name alone cannot answer that, only measured density and power data canCITE:E2.
The 2nm generation also marks a structural break in transistor design, replacing FinFET — the architecture the industry has used for roughly a decade — with Gate-All-Around (GAA) transistorsCITE:E4. Each foundry brands its own GAA implementation: TSMC calls its version Nanosheet, Samsung Electronics calls its version MBCFET, and Intel calls its version RibbonFET, all aimed at tighter current control and lower leakage than FinFETCITE:E4.
Every advanced node generation depends on Extreme Ultraviolet Lithography (EUV) equipment, with a single EUV machine often costing hundreds of millions of dollarsCITE:E6. That cost barrier leaves only three companies — TSMC, Samsung Electronics, and Intel — currently operating at mass-production scale on the leading edge, while Japan's national foundry consortium Rapidus began 2nm trial production in 2025 as an emerging challengerCITE:E6.
TSMC's N2, Samsung Electronics' SF2, and Intel's 18A all enter mass production in the fourth quarter of 2025, converging on the same "2nm generation" label at effectively the same timeCITE:E3.
| Company | Node Name | Transistor Architecture | Mass Production Timing |
|---|---|---|---|
| TSMC | N2 | Nanosheet (GAA) | Q4 2025 |
| Samsung Electronics | SF2 | MBCFET (GAA) | Q4 2025 |
| Intel | 18A | RibbonFET (GAA) | Q4 2025 |
Timing data above reflects foundry process node trackingCITE:E3; architecture naming reflects each company's GAA implementationCITE:E4.
The next differentiation point beyond 2nm is backside power delivery: Intel's 18A introduces a backside power network called PowerVia, and TSMC's A16 (1.6nm), planned for the fourth quarter of 2026, will route power delivery on the back of the wafer separately from signal wiring on the frontCITE:E5. Separating power and signal layers this way is aimed at further gains in efficiency and density beyond what planar scaling alone can deliverCITE:E5.
Taken together, the evidence points to a naming system that stopped tracking physical geometry after the 22nm generation, yet three foundries — TSMC, Samsung Electronics, and Intel — still converge on the same "2nm" label in the same quarter, each using its own branded version of the same underlying GAA architecture shift away from FinFET. That convergence is bounded by a cost barrier: EUV lithography's hundreds-of-millions-of-dollars machine cost is why only three companies operate at mass-production scale, with Rapidus's 2025 trial production the one visible attempt to join them. The next competitive marker already flagged — backside power delivery in Intel's 18A and TSMC's planned Q4 2026 A16 — suggests that as node names lose meaning as a size indicator, structural techniques like backside power delivery become the more concrete signal of generational progress.
Process node names have not corresponded to any single physical transistor dimension since roughly the 22nm generation, and the number in a node name today func…
A smaller node number generally points to higher transistor density and better power efficiency — either faster performance at the same power draw, or the same …
The 2nm generation also marks a structural break in transistor design, replacing FinFET — the architecture the industry has used for roughly a decade — with Gat…
Every advanced node generation depends on Extreme Ultraviolet Lithography (EUV) equipment, with a single EUV machine often costing hundreds of millions of dolla…
The real story here isn't the number "2" — it's that TSMC, Samsung Electronics, and Intel all hit mass production on their respective 2nm-generation nodes in the same quarter while using three differently branded versions of the same GAA architecture shift. That simultaneity, combined with EUV's hundreds-of-millions-of-dollars machine cost limiting the field to three incumbents plus one 2025 challenger in Rapidus, tells you the competitive variable has moved from the node label to execution details the name can't capture. The concrete indicator to watch next isn't whether a future node is called "1.6nm" or something smaller — it's whether TSMC's A16 backside power delivery actually ships on its planned Q4 2026 timeline alongside Intel's PowerVia, since backside power is the first architectural feature in this generation that's independently verifiable rather than just a generation label.
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