TSMC, Intel, and the UCIe Consortium each detail distinct paths to multi-die integration: TSMC's CoWoS interposer exceeds 1,700mm² to pack an SoC with more than four HBM cubes, Intel's EMIB bump pitch scales from 55 to 45 micron, its Foveros Direct 3D copper bonding pitch shrinks from 9 to 3 micron, and UCIe pursues an open chiplet interconnect standard.
How does TSMC's CoWoS platform integrate multiple dies through a large interposer?
TSMC's CoWoS platform uses an interposer larger than 2x the standard reticle size, roughly 1,700mm², to integrate a leading SoC chip with more than four HBM2/HBM2E memory cubes in a single packageCITE:E1. TSMC describes CoWoS as a "wafer level system integration platform" that offers a range of interposer sizes, HBM cube counts, and package sizesCITE:E2.
How does Intel's EMIB bump pitch scaling support high-bandwidth chiplet interconnects?
Intel's second-generation EMIB technology scales bump pitch from 55 micron to 45 micron, enabling high-bandwidth connectivity with either Foveros Direct 3D chiplets or multiple I/O chipletsCITE:E3. Intel states this lets Foundry customers connect chiplets across a package rather than relying on a single monolithic dieCITE:E3.
How does Intel's Foveros Direct 3D copper bonding pitch scaling raise stacked-chiplet interconnect density?
Intel's first generation of Foveros Direct 3D uses copper-to-copper bonding at a 9-micron pitch, and the second generation shrinks that pitch to 3 micronsCITE:E4. This pitch reduction applies to direct 3D die-on-die stacking, distinct from the lateral, interposer-based connections used in EMIB and CoWoSCITE:E4.
How does the UCIe standard drive an open chiplet ecosystem?
The UCIe Consortium states its standard is built to establish "an open ecosystem of chiplets for on-package innovations"CITE:E5. This positions UCIe as a common interconnect specification that packaging platforms such as CoWoS and EMIB/Foveros Direct can build toward, rather than each relying solely on proprietary connectionsCITE:E5.
Packaging metrics compared
| Technology | Entity | Metric | Value |
|---|
| CoWoS interposer | TSMC | Size vs. standard reticle | >2x reticle (~1,700mm²) |
| CoWoS package | TSMC | HBM cubes integrated | More than 4 HBM2/HBM2E cubes |
| EMIB, 2nd generation | Intel | Bump pitch | 55 micron → 45 micron |
| Foveros Direct 3D, 1st→2nd gen | Intel | Copper bonding pitch | 9 micron → 3 micron |
Across the three sources, two distinct geometries emerge for integrating multiple dies once single-die scaling slows. TSMC's CoWoS scales laterally, expanding interposer area to ~1,700mm² to fit an SoC alongside four or more HBM cubesCITE:E1CITE:E2. Intel scales both laterally and vertically: EMIB narrows bump pitch from 55 to 45 micron for chiplet-to-chiplet links on a substrateCITE:E3, while Foveros Direct 3D narrows copper bonding pitch from 9 to 3 micron for direct die-on-die stackingCITE:E4. UCIe's stated goal of an open chiplet ecosystem points toward interconnects that could, in principle, span across such platform-specific approachesCITE:E5.
Author's Take・林紀旭 James Lin
The two vendors are optimizing different axes of the same problem. TSMC's CoWoS scales by area — a ~1,700mm² interposer fitting an SoC plus four-plus HBM cubes — which favors breadth of memory bandwidth per package. Intel is scaling by pitch: EMIB's bump pitch moving from 55 to 45 micron and Foveros Direct 3D's copper bonding pitch moving from 9 to 3 micron both push interconnect density rather than package area. That 3-micron Foveros Direct pitch is the number worth tracking — it is a substantially finer bond pitch than the EMIB bump pitch, and whether it ships in volume will indicate whether direct die-on-die stacking or interposer-based lateral integration becomes the denser path for multi-chiplet designs. Separately, UCIe's open-ecosystem goal only matters in practice if chiplets built to it can actually land inside CoWoS- or EMIB/Foveros-based packages — that cross-platform adoption is the second thing to watch.