TSMC's CoWoS advanced packaging, not logic wafer output, is the binding constraint on AI accelerator supply through 2025–2026. TSMC discloses only growth rates while TrendForce estimates monthly capacity near 120,000–140,000 wafers by end-2026, and TSMC has begun outsourcing overflow to Amkor and ASE Technology because a 18–24 month expansion cycle keeps packaging capacity from catching up with GPU demand.
Why is CoWoS the real bottleneck for AI chips, not the logic wafer itself?
EffectStory's data shows that TSMC's CoWoS 2.5D silicon-interposer packaging, not logic wafer output, is the capacity that actually gates AI accelerator supplyCITE:E1. CoWoS has remained in long-term short supply and near fully booked across 2025–2026CITE:E1. The reason lies in what CoWoS actually does: it integrates a GPU with multiple HBM stacks on a silicon interposer, a process that is technically complex, carries a high yield threshold, and takes 18 to 24 months to expandCITE:E6. Because any single step in that chain can stall, what looks like a "GPU shortage" is frequently a shortage of packaging and HBM capacity insteadCITE:E6.
How large is TSMC's CoWoS capacity, and what do official growth rates versus industry estimates show?
TSMC has never disclosed an absolute CoWoS monthly capacity figure and instead reports only growth rates, while TrendForce separately estimates the physical volumeCITE:E2. Officially, TSMC has stated that CoWoS capacity doubled in 2024 and doubled again in 2025, with a compound annual growth rate above 80% across 2022–2027CITE:E2. TrendForce, an outside research firm, estimates TSMC's CoWoS capacity will reach roughly 120,000–140,000 wafers per month by the end of 2026 — a market estimate, not an official disclosureCITE:E2. TrendForce also reports that the CoWoS supply-demand gap is narrowing, from about 20% short of demand to about 10% by the end of 2026CITE:E2.
How is TSMC responding to excess demand, and why outsource to Amkor and ASE Technology?
Facing demand it cannot fully absorb in-house, TSMC has begun routing part of its CoWoS workload to outside packaging houses, Amkor and ASE TechnologyCITE:E3. Industry estimates put Amkor's 2026 CoWoS-related capacity at roughly 180,000–190,000 wafers per year — an annual figure that is not directly comparable to TSMC's monthly wafer-per-month numbersCITE:E3. Separately, ASE and its Siliconware Precision Industries (矽品) unit are developing their own CoWoP packaging processCITE:E3.
How far can SoIC close the gap left by CoWoS?
SoIC, TSMC's wafer-level 3D hybrid-bonding process, is a distinct technology from CoWoS with a much smaller footprint, estimated at only 10,000–15,000 wafers per month in 2026CITE:E4. Because SoIC and CoWoS are different processes, their wafer counts cannot simply be added togetherCITE:E4. In practice, the two are combined into SoIC+CoWoS packages used for the highest-end AI chips, meaning SoIC supplements CoWoS rather than replacing itCITE:E4.
How does the competitive landscape among Samsung, Intel, and UMC compare in advanced packaging?
Samsung Electronics and Intel are both building rival advanced-packaging platforms, but neither has disclosed capacity figures, and both trail TSMC's share of the 2.5D packaging marketCITE:E5. Samsung Electronics offers I-Cube and H-Cube packagingCITE:E5, while Intel offers EMIB and Foveros and is currently the only integrated device manufacturer (IDM) producing 3D hybrid bonding at volumeCITE:E5. UMC and PSMC (力積電) instead position themselves as niche players, picking up overflow demand rather than competing head-onCITE:E5.
Why can't advanced packaging capacity be expanded quickly, and how does that constrain GPU shipments?
Advanced packaging capacity cannot scale quickly because bonding a GPU to multiple HBM stacks on a silicon interposer requires a complex process with a high yield bar, and expanding that capacity takes 18 to 24 monthsCITE:E6. Because the packaging step sits downstream of chip fabrication, a bottleneck there caps final AI chip shipments regardless of how much logic wafer capacity is availableCITE:E6. That is why supply constraints reported as a "GPU shortage" often trace back to packaging and HBM capacity insteadCITE:E6.
| Metric | Figure | Source |
|---|
| TSMC CoWoS capacity growth (2024, 2025) | Doubled in each year | CITE:E2 |
| TSMC CoWoS CAGR (2022–2027, official) | Above 80% | CITE:E2 |
| TrendForce CoWoS capacity estimate (end-2026) | ~120,000–140,000 wafers/month | CITE:E2 |
| TrendForce CoWoS supply-demand gap (2026) | Narrowing from 20% to 10% | CITE:E2 |
| Amkor CoWoS-related capacity (2026, annual) | ~180,000–190,000 wafers/year | CITE:E3 |
| SoIC capacity estimate (2026) | ~10,000–15,000 wafers/month | CITE:E4 |
| Advanced packaging capacity expansion cycle | 18–24 months | CITE:E6 |
What this means: TSMC's own reported growth — doubling CoWoS output in both 2024 and 2025 at a CAGR above 80% — still was not enough to close the gap on its own, which is why TrendForce's supply-demand shortfall estimate only narrows to 10% by end-2026 and why TSMC is routing an estimated 180,000–190,000 wafers a year to AmkorCITE:E2CITE:E3. SoIC's much smaller 10,000–15,000 wafers-per-month volume shows it functions as a complement for top-end packages rather than a substitute for CoWoS capacityCITE:E4. With Samsung Electronics and Intel unable to disclose comparable capacity and CoWoS-class capacity taking 18–24 months to add, the packaging layer — not the logic wafer — remains the variable that sets the pace of AI chip shipmentsCITE:E5CITE:E6.
Author's Take・林紀旭 James Lin
The capacity math here matters more than any single GPU launch date: TSMC's own growth rate — doubling CoWoS output in both 2024 and 2025 at a CAGR above 80% — still left enough of a gap that TrendForce pegs unmet demand narrowing only to 10% by end-2026, and that improvement is happening largely because Amkor is absorbing roughly 180,000–190,000 wafers a year of overflow. That outsourcing move is the real signal: SoIC+CoWoS combinations can raise efficiency per package, but SoIC's own volume — 10,000–15,000 wafers a month against CoWoS's estimated 120,000–140,000 — confirms it is a supplement, not a substitute, for CoWoS capacity. The metric worth watching next is whether Amkor's and ASE Technology's outsourced volumes keep pace as TSMC's 18–24 month expansion cycle plays out; if third-party output stalls, GPU allocation timelines will move with packaging capacity, not with wafer starts.